1. Field of the Invention:
The present invention relates to a semiconductor device and a method of making the same. The present invention specially concerns a semiconductor device principally comprising MOSFET intended to achieve a higher integration and lower wiring resistance.
2. Description of the Prior Art:
In recent years, in order to achieve higher integration of ICS or LSI, miniaturization of unitary devices and decreasing of wiring resistances have actively been sought.
Generally, in MOS IC or MOS LSI, a polycrystalline silicon pattern, and an aluminum wiring pattern, a provided on a substrate with an insulation film therebetween together with combined diffused regions formed in the substrate, are widely used. However, as the unit devices become smaller, wiring between them and interconnection between the wirings become more difficult. Thus, the wiring and the unit devices are likely to be destroyed during the wiring process. This has been a shortcoming in the manufacturing of semiconductor ICS or LSI.
Firstly, an explanation is made with reference to FIG. 1(a) to FIG. 1(f), which show the prior art steps of manufacturing an N-channel silicon gate MOS LSI as an example embodying the prior art connections between a polycrystalline silicon layer and a diffused region.
Firstly, as shown in FIG. 1(a), on a principal surface of a P-type silicon substrate, isolation regions of a thick film of oxide of silicon are formed by a known selective oxidation method. Then, as shown in FIG. 1(b), gate-oxide film 3 shown in FIG. 1(b) is formed by, for instance, thermal oxidation. Nextly, as shown in FIG. 1(c), a photoresist film of a desired mask pattern for forming the gate-oxide film 3, is formed in order to make an opening 39 on the gate-oxide film 3. This step is carried out by chemical etching using a fluoric acid-fluoroammonium mixed solution. Then, after forming the opening 39 on the oxide film, the photoresist film 4 is removed by a known method, and as shown in FIG. 1(d), a polycrystalline silicon layer 5 is formed thereon. Thereafter, phosphorus is diffused on the polycrystalline layer 5 by a known thermal diffusion method, thereby to increase electric conductivity. Simultaneously, phosphorus is diffused in the substrate 1 to form a N.sup.+ -diffused region 6, which is to be connected to the polycrystalline layer 5. Then, as shown in FIG. 1(e ), the polycrystalline silicon layer 5 is etched to a predetermined pattern. Then as shown in FIG. 1(f), by utilizing this polycrystalline silicon layer 5 as a mask, N.sup.+ -diffusion regions 7 which become source and drain are formed in the substrate 1 by ion-implanting phosphorus or arsenic by the known method, and an interlayer insulation film 8 is formed thereon. After forming electrode contact openings on the insulation films 8, 3, aluminum alloy electrodes 9 are formed therein, and then protection film 10 is formed thereon.
In case a semiconductor device would comprise double-layered polycrystalline silicon layers. Connections between the first polycrystalline silicon layer and the diffused region on the substrate and connection between the second polycrystalline silicon layer and the diffused region on the substrate and connection between the first polycrystalline layer and the second polycrystalline layer would be made in accordance with the preceding prior art example. Accordingly, in such a double-layered polycrystalline silicon structure, the steps of forming opening in the insulation film, become necessarily doubled in number.
As has been described, the prior art making of the MOS FET uses lithographic etching of the gate-oxide film. Therefore when the photoresist film has a pinhole or a similar defect, the gate-oxide film that is obtained will correspondingly have a pinhole or similar defect this pinhole in the the gate-oxide film resultantly, will shortcircuit the substrate and the polycrystalline silicon film. Furthermore, removing of the photoresist film after the etching is made by immersing the substrate into fuming nitric acid or a the like substance to be used for the resist removal or by applying. oxygen, plasma etching. Accordingly, the gate-oxide film is likely to be polluted with heavy metal or the like impurities in the etching agent or in the photoresist. Furthermore, the prior art method makes thin oxide film, of about 1 nm on the surface of the silicon substrate. Accordingly, there is a necessity to remove the thin oxide film by chemical etching by fluoric acid prior to formation of polycrystalline silicon layer on the substrate before the formation of polycrystalline silicon layer. And at this step the gate-oxide-film is also etched to some extent. Therefore, irregular parts may be formed on the surface of the gate-oxide film, and such influence is especially adverse when the gate-oxide film becomes thinner as the individual element of the IC or LSI becomes designed smaller.